
PCI-DAS1002 User's Manual Specifications
21
Counters
Table 9. Counter specifications
Two 82C54 devices. 3 down counters per 82C54, 16 bits each
Counter 0 - ADC residual
sample counter
Source: ADC Clock
Gate: Internal programmable source
Output: End-of-Acquisition interrupt
Counter 1 - ADC pacer lower
divider
Source: 10 MHz oscillator
Gate: Tied to counter 2 gate, programmable source
Output: Chained to counter 2 clock
Counter 2 - ADC pacer upper
divider
Source: Counter 1 output
Gate: Tied to counter 1 gate, programmable source
Output: ADC pacer clock (if software selected). Available at
user connector.
Counter 0 - pretrigger mode
Source: ADC clock
Gate: External trigger
Output: End-of-Acquisition interrupt
Counter 0 - user counter 4
(when in non-pretrigger mode)
Source: User input at 100-pin connector (CTR4 CLK)
or internal 10 MHz (software selectable)
Gate: User input at 100-pin connector (CTR4 GATE)
Output: Available at 100-pin connector (CTR4 OUT)
Counter 1 - user counter 5
Source: User input at 100-pin connector (CTR5 CLK)
Gate: User input at 100-pin connector (CTR5 GATE)
Output: Available at 100-pin connector (CTR5 OUT)
Counter 2 - user counter 6
Source: User input at 100-pin connector (CTR6 CLK)
Gate: User input at 100-pin connector (CTR6 GATE)
Output: Available at 100-pin connector (CTR6 OUT)
High pulse width (clock input)
Low pulse width (clock input)
Crystal oscillator frequency
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