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Clear (Pin 41)
The Clear output can be pulsed for approximately 50 microseconds after a Device Clear (DCL), Selected
Device Clear (
SDC), or Interface Clear (IFC) command has been sent on the bus, determined by the Form
(
F) mode of each channel. Execution of an SDC to either channel or a DCL affects both channels.
effect depends o
at
The
n whether either channel is in the High Speed Binary (
F5) mode. If in the F5 mode, the
SCII
both
ot pulsed. If neither channel is in the
F5 mode, an SDC DCL returns
ls to their power-up configuration and pulses both Clear lines for approximately 50
s.
The Clear line is normally active high. The Invert (
I) command programs it active low (I8). The
Handshake (
H) command can pulse the Clear line of either channel (H0), independent of any I/O
operations.
Data Strobe (Pin 42)
channels in this mode have their command interpreter re-enabled and then they are returned to the A
Hexadecimal (
F0) mode. All other parameters remain unchanged. In addition, the Clear lines on
channels are n
to either channel or a
both channe
microsecond
The Data Strobe output is pulsed for approximately 50 microseconds after new data are output on the I/O
port. The Data Strobe line is normally active high, but ay be programmed active low (
I4) by the Invert
O
.
Trigger (Pin
m
(
I) command. The Handshake (H) command can pulse the Data Strobe line (H1), independent of any I/
operations. The Data Strobe output is not pulsed when Bit Set (
A) or Bit Clear (B) commands are executed
43)
The Trigger output is pulsed for approximately 50 microseconds after a Group Execute Trigger (GET)
command is received from the bus controller. The trigger pulse is normally active high, but can be made
active low (
I2) with the Invert (I) command. The Handshake (H) command can independently pulse the
Trigger line (
H2), independent of any bus activity.
30 Digital488/80A Operation Digital488/80A User's Manual
- User's Manual 1
- Introduction to this Manual 3
- Table of Contents 4
- 7 - Troubleshooting 5
- A - Appendix A 5
- B - Appendix B 5
- Digital488/80A Overview 1 7
- Accessories 8
- Specifications 9
- CAUTION 10
- Data Transfer Speeds 10
- Digital488/80A Setup 2 11
- Hardware Setup 12
- Default DIP Switch Settings 13
- Addressing Mode Selection 13
- Secondary Address Settings 14
- HVCX1 Option Setup 16
- WARNING 16
- Digital I/O Ports 23
- Introduction 25
- Line Voltage Selection 26
- Fuse Replacement 28
- Rack Mount 29
- Bench Top 29
- Power-Up Activation 30
- Programming Examples 31
- C0 is in use 33
- C) command C5 was executed 33
- Digital488/80A Operation 4 35
- Clear (Pin 41) 36
- Data Strobe (Pin 42) 36
- Trigger (Pin 36
- Inhibit (Pin 44) 37
- Service (Pin 45) 37
- External Data Ready (Pin 46) 37
- IEEE 488 Bus Support 38
- Bus Addresses 40
- Bus Terminators 40
- IEEE 488 Background 5 41
- Bus Lines & Bus Commands 42
- Handshake Lines 43
- Data Transfer Lines 43
- Bus Command Groups 44
- More On Service Requests 45
- Digital488/80A Commands 6 47
- Command Syntax 48
- Command Set & Support 49
- Command Summary 50
- - SRQ on Ready 51
- Command Reference 52
- A - Bit Set 53
- B - Bit Clear 54
- C - Configuration 55
- D - Data Output 56
- E? - Query Error Status 57
- F - Data Format 59
- G - Bus Input/Output 63
- H - Handshake 64
- I - Invert 65
- K - End-Or-Identify 66
- L - Buffer 67
- M - Service Request Mask 68
- O - Recall Configuration 69
- P - Port Select 70
- Q - Inhibit 71
- R - Data Ready 72
- S - Save Configuration 73
- T - Test 74
- U - User Status 75
- V - View Configuration 78
- V? - View Version 79
- X - Execute 80
- Y - Bus Terminator 81
- ? - Query 82
- Serial Poll Status Byte 83
- Troubleshooting 7 85
- Buffer Overrun 86
- Query Error Status 86
- Appendix A A 87
- Software Setup 88
- Appendix B B 91
- IEEE 488 Bus Commands 92
- ASCII Codes 93
- ASCII Code Details 95
- Abbreviations 104
- Notes 106
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