Measurement-computing CIO-PDMAxx Bedienungsanleitung PDF herunterladen (Seite 13)

Ports A & B are set to input on power-up or hardware reset of the computer. The

direction of transfer, input/output, is controlled by one bit for each port in BASE + 2.

The inputs of the ports are one TTL load. The outputs can sink 24mA on output low. .

When the ports are configured for output and a read back is executed, the actual data

on the pins is read back. This may differ from what was written to the port if a chip is

faulty or a digital line is short circuited.

PORT A DATA

BASE ADDRESS + 0 300h, 768

Pin 19Pin 18Pin 17Pin 16Pin 15Pin 14Pin 13Pin 12

A0A1A2A3A4A5A6A7

01234567

PORT B DATA

BASE ADDRESS + 1 301h, 769

Pin 11Pin 10Pin 9Pin 8Pin 7Pin 6Pin 5Pin 4

B0B1B2B3B4B5B6B7

01234567

5.1.2 DMA CONTROL REGISTER

DMA control

BASE ADDRESS + 2 302h, 770

Pin 37Pin 29N/AN/APin 24Pin 25N/AN/A

PORT A

DIR

PORT B

DIR

BYTE/

WORD

XFER

SOURCE

AUX1AUX2DMA

LEVEL

DMA

ENABLE

01234567

Output1

Input0PORT A DIR

Output1

Input0PORT B DIR

Word transfers1

Byte transfers0BYTE/WORD

Internal - 8254 timer1

External - from Transfer Req In, pin 2.0XFER SOURCE

Output only on pin 24XAUX1

Output only on pin 25XAUX2

Level 3 (channel 3)1

Level 1 (channel 1)0DMA LEVEL

Enabled1

Disabled0DMA ENABLE

FUNCTIONVALUEBIT NAME

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 31 32

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